Static random access memory (SRAM) is a type of volatile semiconductor memory that stores data bits using bistable circuitry that does not need refreshing. An SRAM cell may be referred to as a bit cell because it stores one bit of information, represented by the logic state of two cross coupled inverters. Memory arrays include multiple bit cells arranged in rows and columns. Each bit cell in a memory array typically includes connections to a power supply voltage and to a reference voltage. Logic signals on bit lines control reading from and writing to a bit cell, with a word line controlling connections of the bit lines to the inverters, which otherwise float. A word line may be coupled to the bit cells in a row of a memory array, with different word lines provided for different rows.
Each successive bit cell along a bit line or word line has a characteristic input capacitance, and each conductor leg between bit cells has a resistance, leading to a signal propagation delay. The delay is longer for bit cells that are farther than others along signal paths beginning at the source of memory addressing and control signals, such as the outputs of address decoding gates and line drivers coupled at an edge of the memory array. The delay affects the time needed to access the bit cells and limits the highest frequency at which the memory can be operated. The time taken to access an SRAM bit cell, e.g., for a read operation, may vary due to several factors including the relative position of the accessed bit cell within the SRAM array, and also including variation in the operational characteristics of SRAM components such as transistors in bit cells, the latter typically being a result of variations in the semiconductor production process as opposed to bit cell location. Reliable estimation of SRAM timing characteristics is important for ensuring consistency in system components and high system performance.